DocumentCode
1841630
Title
Electrical modeling of the chip scale BGA
Author
Caggiano, Michael F. ; Brush, R.M. ; Kleban, J.T. ; Chuaypradit, P.J.
Author_Institution
Dept. of Electr. & Comput. Eng., Rutgers Univ., Piscataway, NJ, USA
fYear
1998
fDate
25-28 May 1998
Firstpage
1280
Lastpage
1285
Abstract
The CSBGA package-modeling program can rapidly generate a model from a specific description of a package or from partial information when only a rough approximation is needed. This innovative new software is targeted for the engineer who, at his desktop PC or workstation, can rapidly generate an accurate electrical model of a chip scale BGA. Program operation consists of entering the available data, and retrieving output that can be used in a simulation, or simply analyzed for an idea as to the range of values the parasitic effects take. The whole process will just take minutes. The program was designed to be fast and portable contrasting other methods of modeling in which such attributes were sacrificed for greater accuracy. Such accuracy may not be desired in most applications where there is a greater emphasis on speed or where powerful workstations are not available. The models targeted for both data processing and RF systems will have a wide range of use across military and commercial electronics applications
Keywords
C language; ball grid arrays; chip scale packaging; digital simulation; integrated circuit modelling; CSBGA; RF systems; accurate electrical model; chip scale BGA; commercial electronics; data processing; package-modeling program; parasitic effects; simulation; Analytical models; Brushes; Capacitance; Data processing; Electronics packaging; Inductance; Information retrieval; Power system modeling; Radio frequency; Workstations;
fLanguage
English
Publisher
ieee
Conference_Titel
Electronic Components & Technology Conference, 1998. 48th IEEE
Conference_Location
Seattle, WA
ISSN
0569-5503
Print_ISBN
0-7803-4526-6
Type
conf
DOI
10.1109/ECTC.1998.678906
Filename
678906
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