Title :
A 0.18-μm CMOS clock and data recovery circuit with reference-less dual loops
Author :
Li, Miao ; Kwasniewski, Tad ; Wang, Shoujun
Author_Institution :
Dept. of Electron., Carleton Univ., Ottawa, ON
Abstract :
A half-rate reference-less clock and data recovery circuit is proposed, incorporating a coarse frequency-locked loop and a fine phase-locked loop with smooth switching to prevent adverse interaction and false locking. Fabricated in a 0.18-mum CMOS process, the recovered clock exhibits a peak-to- peak jitter of 60 ps for a 2-Gb/s PRBS-7 data and a phase noise of -93.5 dBc/Hz at 1-MHz offset. The core circuit consumes 40 mW at 1.8-V supply and occupies an area of 0.3 mm2.
Keywords :
CMOS integrated circuits; frequency locked loops; jitter; phase locked loops; synchronisation; CMOS process; clock recovery; data recovery circuit; fine phase-locked loop; frequency-locked loop; jitter; size 0.18 mum; switching; Charge pumps; Clocks; Delay; Frequency locked loops; Phase detection; Phase frequency detector; Phase locked loops; Switching circuits; Voltage control; Voltage-controlled oscillators;
Conference_Titel :
Circuits and Systems, 2008. ISCAS 2008. IEEE International Symposium on
Conference_Location :
Seattle, WA
Print_ISBN :
978-1-4244-1683-7
Electronic_ISBN :
978-1-4244-1684-4
DOI :
10.1109/ISCAS.2008.4541928
