DocumentCode :
1842196
Title :
System-level HW/SW co-simulation framework for multiprocessor and multithread SoC
Author :
Chung, Moo-Kyoung ; Yang, Sangjun ; Lee, Sang-Heon ; Kyung, Chong-Min
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., KAIST, Daejeon, South Korea
fYear :
2005
fDate :
27-29 April 2005
Firstpage :
177
Lastpage :
180
Abstract :
C/C++-based languages such as SystemC or SpecC can be used for both hardware and software description by raising the level of abstraction for hardware. This paper proposes techniques for fast and accurate high-level co-simulation for multithread and multiprocessor SoC design using SystemC for hardware and legacy C with RTOS (real-time operating system) API for software. Automatically modified legacy C synchronizes with SystemC clock events, and communicates with other modules through IO (input/output) variables and transaction level bus models. Generic RTOS scheduler and POS1X APIs are also provided for the real-time application. About three times faster co-simulation speed than the ISS-based co-simulation along with various profiling data with 95% accuracy were achieved.
Keywords :
C++ language; circuit simulation; hardware-software codesign; microprocessor chips; system-on-chip; C language; C++ language; POSIX API; RTOS scheduler; SoC design; SpecC; SystemC; clock events; cosimulation framework; hardware description; high-level co-simulation; legacy C; multiprocessor; multithread SoC; real-time operating system; software description; Application software; Clocks; Communication system software; Hardware; Operating systems; Real time systems; Software debugging; Software systems; Synchronization; System-on-a-chip;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Design, Automation and Test, 2005. (VLSI-TSA-DAT). 2005 IEEE VLSI-TSA International Symposium on
Print_ISBN :
0-7803-9060-1
Type :
conf
DOI :
10.1109/VDAT.2005.1500049
Filename :
1500049
Link To Document :
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