System identification -based reduced-code testing for pipeline ADCs’ linearity test

This work presents a system identification-based reduced-code testing method for pipeline ADC´s linearity test. In the method, the pipeline ADC under test is identified by characterizing the two most critical parameters in each stage, the stage gain and the comparator offset. The transfer function is investigated to obtain the effects of the gain error and comparator offset on ADC´s linearity performance. With the measurements of a small set of specific transition levels or code bin widths, the system parameters of interest can be achieved using only straightforward linear calculations. The identified model is then used to compute the ADC´s full-code linearity performance. Comparing to standard histogram-based full-code linearity test methods, the proposed method can reduce the data capture time by a factor of several hundreds without appreciably degrading the testing accuracy. Both simulation results and experimental results are included to demonstrate the efficacy of the proposed method.