Power-supply-variation-aware timing analysis of synchronous systems

With state of the art technology scaling, the problem of delay variability due to power supply variations is becoming more and more critical. This paper addresses the problem of analyzing the speed degradation in synchronous systems caused by power supply IR-drop in deep submicron CMOS devices. Considering the impact of power supply variation on the clock skew value, violations of the timing constraints equations are presented. To satisfy the timing constraints over a range of 20% of V_DD variation, a 42% increase in the operational clock period has to be met with circuits operating at 2 GHz and implemented on 65 nm CMOS technology.