Title :
The matrix transform chip
Author_Institution :
AT&T Bell Labs., Holmdel, NJ, USA
Abstract :
The matrix transform chip (MTC) is designed to perform matrix computations of the form Y=UDV where D is the input data matrix of 16-bit twos complement fixed-point numbers and U, V, are arbitrary coefficient matrices of the same precision. The data matrix D is input to the chip in raster scanned order at a maximum sample rate of 40 MHz, and the output matrix is provided in the same order. On a single chip, the maximum dimension of all matrices must be less than eight, but multiple chips can be cascaded to obtain arbitrary dimensions. The MTC consists of 16 16-bit parallel multipliers/40-bit accumulators, a kilobyte of dual-ported transposition static RAM, and a kilobyte of coefficient static RAM, arranged to interact in a regular iterative architecture. At peak operation, the MTC is capable of performing 0.64 billion fixed-point multiples, 0.64 billion 40-bit accumulates, along with 1.92 billion pseudorandom memory-access operations per second
Keywords :
digital arithmetic; matrix algebra; multiplying circuits; random-access storage; 16 bits; accumulators; arbitrary coefficient matrices; coefficient static RAM; dual-ported transposition static RAM; fixed-point multiples; input data matrix; iterative architecture; matrix computations; matrix transform chip; output matrix; parallel multipliers; pseudorandom memory-access operations; raster scanned order; twos complement fixed-point numbers; Arithmetic; CMOS technology; Discrete cosine transforms; Discrete transforms; Engines; Frequency; Graphics; Image coding; Random access memory; Read-write memory;
Conference_Titel :
Computer Design: VLSI in Computers and Processors, 1989. ICCD '89. Proceedings., 1989 IEEE International Conference on
Conference_Location :
Cambridge, MA
Print_ISBN :
0-8186-1971-6
DOI :
10.1109/ICCD.1989.63334
