DocumentCode :
1842818
Title :
Extended counting ADC for 32-channel neural recording headstage for small animals
Author :
Yun, Xiao ; Stanacevic, Milutin
Author_Institution :
Dept. of Electr. & Comput. Eng., Stony Brook Univ., Stony Brook, NY
fYear :
2008
fDate :
18-21 May 2008
Firstpage :
2510
Lastpage :
2513
Abstract :
Extended counting analog-to-digital converter (ECADC) combines the accuracy of delta-sigma modulation and the speed of algorithmic conversion. This conversion architecture is shown to be useful in biomedical applications, where both resolution and speed are demanded. This work presents a design of ECADC for 32 neural recording channels. Several power optimizing methods are described. The designed converter achieves a resolution of 13 bits and a sampling frequency of 512 kHz. With 3.3 V supply, the total power consumption is estimated to be 7 mW. The whole system including 32 neural recording channels is fitted in an area of 3 mm times 3 mm in 0.5 mum CMOS process.
Keywords :
CMOS integrated circuits; analogue-digital conversion; delta-sigma modulation; neural nets; 32-channel neural recording headstage; CMOS process; algorithmic conversion; analog-to-digital converter; delta-sigma modulation; extended counting ADC for; frequency 512 kHz; neural recording channels; power 7 mW; size 0.5 mum; voltage 3.3 V; Analog-digital conversion; Animals; Application software; CMOS process; Clocks; Computer architecture; Delta-sigma modulation; Energy consumption; Sampling methods; Signal processing algorithms;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems, 2008. ISCAS 2008. IEEE International Symposium on
Conference_Location :
Seattle, WA
Print_ISBN :
978-1-4244-1683-7
Electronic_ISBN :
978-1-4244-1684-4
Type :
conf
DOI :
10.1109/ISCAS.2008.4541966
Filename :
4541966
Link To Document :
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