• DocumentCode
    1842822
  • Title

    Architecture design of MPEG-4 texture decoder supporting object-based video coding

  • Author

    Hui-Cheng Hsu ; Chang, Nelson Yen-Chung ; Tian-Sheuan Chang

  • Author_Institution
    Dept. of Electron. Eng., National Chiao Tung Univ., Hsinchu, Taiwan
  • fYear
    2005
  • fDate
    27-29 April 2005
  • Firstpage
    275
  • Lastpage
    278
  • Abstract
    Handling of the complexity which arises due the irregularity data nature for MPEG-4 object based video coding is an important issue in MPEG-4 texture decoder design. Another crucial issue is designing an efficient architecture to satisfy the resource sensitive nature of portable embedded video codec systems. This paper presents an architecture for texture decoding to address these two major issues. By adopting zero-skipping and zero index tables together, the throughput and power consumption are improved significantly. To avoid incurring extra hardware overhead, multiplication sharing and buffer sharing are also incorporated. The synthesized design can perform texture decoding of CIF@30FPS under 2.18 MHz. using UMC 0.18μm 1P6M technology, the reported power consumption is 0.92 mW.
  • Keywords
    digital signal processing chips; image texture; logic circuits; low-power electronics; system-on-chip; variable length codes; video codecs; 0.18 micron; 0.92 mW; CIF@30FPS; MPEG-4 texture decoder; decoder architecture design; embedded video codec systems; object-based video coding; texture decoding; zero index tables; zero skipping; Costs; Decoding; Embedded system; Energy consumption; Hardware; MPEG 4 Standard; Scheduling; Throughput; Video codecs; Video coding;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Design, Automation and Test, 2005. (VLSI-TSA-DAT). 2005 IEEE VLSI-TSA International Symposium on
  • Print_ISBN
    0-7803-9060-1
  • Type

    conf

  • DOI
    10.1109/VDAT.2005.1500074
  • Filename
    1500074