DocumentCode :
1842847
Title :
JPEG2000 encoder architecture design with fast EBCOT algorithm
Author :
Tsai, Tsung-Han ; Tsai, Lian-Tsung
Author_Institution :
Dept. of Electr. Eng., National Central Univ., Chung-Li, Taiwan
fYear :
2005
fDate :
27-29 April 2005
Firstpage :
279
Lastpage :
282
Abstract :
This paper presents an architecture design for JPEG2000 with a fast algorithm in EBCOT. The EBCOT algorithm takes advantages of resolution and SNR scalability together with a random access property, but its complexity also becomes the bottleneck of JPEG2000. In this paper, the authors proposed a fast algorithm that uses two speed-up methods for EBCOT context modeling. The gate counts of JPEG2000 design is about 105.9 K gate with TSMC 0.25 μm technology. It can encode 4.2 million pixels per second at 40 MHz.
Keywords :
computational complexity; digital signal processing chips; image coding; integrated circuit design; logic circuits; low-power electronics; parallel architectures; 0.25 micron; 40 MHz; EBCOT algorithm; JPEG2000 encoder; SNR scalability; architecture design; context modeling; random access property; Algorithm design and analysis; Discrete wavelet transforms; Encoding; Feedback loop; Filters; Frequency domain analysis; Image coding; Pipelines; Quantization; Transform coding;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Design, Automation and Test, 2005. (VLSI-TSA-DAT). 2005 IEEE VLSI-TSA International Symposium on
Print_ISBN :
0-7803-9060-1
Type :
conf
DOI :
10.1109/VDAT.2005.1500075
Filename :
1500075
Link To Document :
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