DocumentCode :
1843221
Title :
Novel test structure to study junction leakage current
Author :
Koike, N. ; Tominaga, K.
Author_Institution :
Matsushita Electron. Corp., Kyoto, Japan
fYear :
1990
fDate :
5-7 March 1990
Firstpage :
213
Lastpage :
216
Abstract :
A test structure for studying the junction leakage current independently of the additional leakage current induced by the process steps for the formation of the diffusion region under contacts is introduced. The test structures purpose is to evaluate the dynamic random access memory (DRAM) process in relation to the DRAM refresh time; it allows the junction leakage current in a certain voltage range, to be measured independently of the additional leakage current caused by the diffusion region under contacts. The structure is applied to the measurements in narrow diffusion regions, and it is shown that, the junction leakage current is induced mainly by local oxidation of silicon (LOCOS) oxide edge stress.<>
Keywords :
MOS integrated circuits; integrated circuit technology; integrated circuit testing; integrated memory circuits; leakage currents; oxidation; random-access storage; DRAM process evaluation; DRAM refresh time; LOCOS; dynamic random access memory; independent of additional leakage; junction leakage current; local oxidation of silicon; measurements in narrow diffusion regions; oxide edge stress; test structure; Current measurement; DRAM chips; Leakage current; Oxidation; Random access memory; Silicon; Stress measurement; Testing; Time measurement; Voltage;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Microelectronic Test Structures, 1990. ICMTS 1990. Proceedings of the 1990 International Conference on
Conference_Location :
San Diego, CA, USA
Type :
conf
DOI :
10.1109/ICMTS.1990.67905
Filename :
67905
Link To Document :
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