Novel test structure to study junction leakage current

A test structure for studying the junction leakage current independently of the additional leakage current induced by the process steps for the formation of the diffusion region under contacts is introduced. The test structures purpose is to evaluate the dynamic random access memory (DRAM) process in relation to the DRAM refresh time; it allows the junction leakage current in a certain voltage range, to be measured independently of the additional leakage current caused by the diffusion region under contacts. The structure is applied to the measurements in narrow diffusion regions, and it is shown that, the junction leakage current is induced mainly by local oxidation of silicon (LOCOS) oxide edge stress.<>