DocumentCode
1843244
Title
Architectural analyses of K-Means silicon intellectual property for image segmentation
Author
Chen, Tse-Wei ; Sun, Chih-Hao ; Bai, Jiun-Ying ; Chen, Han-Ru ; Chien, Shao-Yi
Author_Institution
Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei
fYear
2008
fDate
18-21 May 2008
Firstpage
2578
Lastpage
2581
Abstract
K-means is a clustering algorithm that is widely applied in many fields, including pattern classification, multimedia analysis, and image retrieval. Due to real-time requirements of image segmentation in embedded systems, it is necessary to accelerate K-means algorithm by hardware implementations. The contribution of this paper includes a series of K-means hardware analyses and a newly proposed SIP for image segmentation in SoC environments. Experiments show that the proposed SIP has the maximum clock speed 200 MHz with TSMC 0.18 mum technology, and that it can be successfully used for image segmentation on an FPGA board with AMBA AHB.
Keywords
embedded systems; image segmentation; logic design; system-on-chip; K-means algorithm; K-means hardware analysis; SoC environment; architectural analysis; embedded system; frequency 200 MHz; image segmentation; silicon intellectual property; size 0.18 mum; Algorithm design and analysis; Clustering algorithms; Hardware; Image analysis; Image retrieval; Image segmentation; Intellectual property; Pattern analysis; Pattern classification; Silicon;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2008. ISCAS 2008. IEEE International Symposium on
Conference_Location
Seattle, WA
Print_ISBN
978-1-4244-1683-7
Electronic_ISBN
978-1-4244-1684-4
Type
conf
DOI
10.1109/ISCAS.2008.4541983
Filename
4541983
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