Title :
A fast floor planning algorithm for architectural evaluation
Author :
McFarland, Michael C.
Author_Institution :
AT&T Bell Labs., Murray Hill, NJ, USA
Abstract :
A method for producing a chip floor plan from a list of blocks and their interconnections is presented. The blocks can be of different sizes, and each block can have several possible aspect ratios. The algorithm places the blocks and chooses the orientation and aspect ratio of each to produce a near-minimum area floor plan. The preliminary placement of the blocks is done using a standard min-cut placement algorithm, modified so that it can handle blocks of different sizes. The choice of aspect ratio and orientation is done using a dynamic programming algorithm, along with a heuristic that limits the number of possible configurations explored. The algorithm is shown to give near-optimal results, yet it is faster than comparable placement algorithms, fast enough to be used in the inner loop of a program that generates and evaluates many alternative designs for a given high-level behavioral specification
Keywords :
circuit layout CAD; dynamic programming; monolithic integrated circuits; architectural evaluation; aspect ratio; aspect ratios; blocks; chip floor plan; dynamic programming algorithm; fast floor planning algorithm; heuristic; high-level behavioral specification; inner loop; interconnections; near-minimum area; orientation; standard min-cut placement algorithm; Algorithm design and analysis; Costs; Delay effects; Dynamic programming; Educational institutions; Geometry; Heuristic algorithms; Multiplexing; Very large scale integration; Wiring;
Conference_Titel :
Computer Design: VLSI in Computers and Processors, 1989. ICCD '89. Proceedings., 1989 IEEE International Conference on
Conference_Location :
Cambridge, MA
Print_ISBN :
0-8186-1971-6
DOI :
10.1109/ICCD.1989.63336