Performance Optimization of Ka-Band MMIC Power Amplifier Using On-Wafer Pulsed Power Test

A novel technique has been developed to optimize the power MMIC performance by using on-wafer pulsed power test. Traditionally, only dc parameters were used to determine the chip operating bias condition. The on-wafer test was used to determine the functionality of the device, and the MMIC chip performance is optimized through manual bias tuning at module level. This technique provides significant cost savings in high volume production environment.