DocumentCode
1843869
Title
Design implications of low-K
Author
Sánchez, Héctor
Author_Institution
Adv. Circuits Dev. Center, Motorola, Austin, TX, USA
fYear
2003
fDate
2-4 June 2003
Firstpage
3
Lastpage
5
Abstract
The aggressive technology migration of the last 10 years is presented. The circuit-level electrical characteristics of interest ( performance, power, area, noise ) that drive the definition of the back-end of line (BEOL) architecture features ( material, width, pitch, space ) are discussed. The paper finishes with a portrayal of the system, circuit, and technology options that may be needed in the 65 nm to 45 nm technology nodes to maintain scalability.
Keywords
capacitance; dielectric materials; integrated circuit design; integrated circuit interconnections; metallisation; noise; scaling circuits; 65 to 45 nm; BEOL; aggressive technology migration; back-end line architecture; circuit-level electrical properties; electrical noise; low dielectric constant implication design; metallisation; scalability; system portrayal; Capacitance; Delay; Design optimization; Dielectric materials; Integrated circuit interconnections; Metallization; Paper technology; Routing; Space technology; Wires;
fLanguage
English
Publisher
ieee
Conference_Titel
Interconnect Technology Conference, 2003. Proceedings of the IEEE 2003 International
Print_ISBN
0-7803-7797-4
Type
conf
DOI
10.1109/IITC.2003.1219695
Filename
1219695
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