Title :
Fundamental, integration, and reliability of the 90 nm generation Cu/LK(k=2.5) damascene using a novel PECVD porous low-k dielectric film
Author :
Yang, Y.L. ; Li, L.P. ; Ouyang, H. ; Lu, Y.C. ; Lu, H.H. ; Lin, C.H. ; Lin, K.C. ; Jang, S.M. ; Liang, M.S.
Author_Institution :
Dept. of Dielectrics & CMP, Taiwan Semicond. Manuf. Co., Hsin-Chu, Taiwan
Abstract :
A novel PECVD porous low-k material with k=2.5, LK(k=2.5), has been successfully integrated with Cu for 90 nm generation BEOL interconnect technology on 300 mm wafers. Fundamental film studies showed that this low-k material is thermally stable up to 400°C and can be strongly adhered to various dielectric films. Electrical measurement results from the Cu/LK(k=2.5) damascene interconnect showed tight and 100%-yielded distributions in 0.12/0.12 μm interline leakage, one million 0.13 μm viachain via Rc and 0.12 μm Cu line Rs. To maximize the Cu/LK(k=2.5) interconnect capacitance performance, no middle etch stop layer and no top CMP cap were used in the dielectric film stacking. The final k value of the LK(k=2.5) after integration was retained at 2.5 using an optimized PR ashing chemistry by comparing the Cu/LK(2.5) 0.12/0.12 μm interline capacitance to a Cu/LK(3.0) one. The intrinsic BEOL time dependent dielectric breakdown (TDDB) lifetime, T63, of the Cu/LK(k=2.5) is predicted to be 4.56×108 yrs at 0.3 MV/cm and 125°C. Further reliability evaluations of the Cu/LK(k=2.5) in electromigration (EM) and stress migration (SM) showed that its predicted T0.1 EM lifetimes for 0.12 μm Cu line or 0.13 μm via at 1 MA/cm2 and 110°C are 152k hrs or 144k hrs, and its SM failure rate (>10% shift in Rc) is zero after 500hr annealing at 175°C. Finally, the packaging feasibility of this Cu/LK(k=2.5) damascene interconnect was also demonstrated using current wire bonding technologies.
Keywords :
annealing; capacitance; copper; current density; dielectric materials; dielectric thin films; electric breakdown; electromigration; integrated circuit bonding; integrated circuit interconnections; integrated circuit packaging; integrated circuit reliability; lead bonding; leakage currents; nanoporous materials; plasma CVD coatings; thermal stability; yield stress; 0.12 micron; 0.13 micron; 110 degC; 125 degC; 175 degC; 300 mm; 400 degC; 500 hr; 90 nm; BEOL interconnect technology; Cu; Cu/low k damascene interconnect; PECVD porous low-k dielectric film; annealing; capacitance; current density; current wire bonding; dielectric breakdown; dielectric film stacking; electrical measurement; electromigration; leakage currents; packaging feasibility; reliability; stress migration failure; thermal stability; yield stress; Capacitance measurement; Chemistry; Dielectric breakdown; Dielectric films; Dielectric materials; Dielectric measurements; Electric variables measurement; Etching; Samarium; Stacking;
Conference_Titel :
Interconnect Technology Conference, 2003. Proceedings of the IEEE 2003 International
Print_ISBN :
0-7803-7797-4
DOI :
10.1109/IITC.2003.1219698