A low-voltage CMOS low-dropout regulator with novel capacitor-multiplier frequency compensation

This paper presents a low-voltage, low-quiescent current, low-dropout voltage regulator (LDO) with a novel capacitor-multiplier frequency compensation technique. The proposed compensation strategy can make the LDO stable under the entire load-current range without relying on an ESR zero. By eliminating cascode structure or buffer stage, the proposed LDO facilitates low voltage operation. Moreover, the capacitor-multiplier circuit reduces the on-chip compensation capacitor greatly and can be effectively realized without extra current budget. Implemented in a 0.18-mum CMOS technology, the LDO is able to provide 200 mA load current with 160 mV dropout voltage while consuming only 20 muA ground current. With a 1 muF output capacitor, the load-transient output variation is 17 mV through maximum current step changes. The on-chip compensation capacitor is reduced to 1 pF.