90 nm generation, 300 mm wafer low k ILD/Cu interconnect technology

Author

Jan, C.-H. ; Bielefeld, I. ; Buehler, M. ; Chikamane, V. ; Fischer, K. ; Hepburn, T. ; Jain, A. ; Jeong, Joonsoo ; Kielty, T. ; Kook, S. ; Marieb, T. ; Miner, B. ; Nguyen, P. ; Schmitz, A. ; Nashner, M. ; Scherban, T. ; Schroeder, B. ; Wang, P.-H. ; Wu, R

Author_Institution

Logic Technol. Dev., Intel Corp., Hillsboro, OR, USA

fYear

2003

fDate

2-4 June 2003

Firstpage

15

Lastpage

17

Abstract

This paper presents a 90 nm generation and 300 mm wafer size interconnect technology with 7 layers of Cu metallization and low k ILD. Carbon doped oxide (CDO) low k ILD is used to achieve > 20% inter- and intra-layer capacitance improvement and 25-30% RC improvement over 130 nm generation SiOF interconnect process with equivalent electromigration performance.

Keywords

capacitance; carbon compounds; copper; electromigration; interconnections; metallisation; permittivity; silicon compounds; 300 mm; 90 nm; CO-Cu; Cu metallization; SiOF interconnects; SiOF-Cu; capacitance; electromigration; interconnect technology; low k carbon doped oxide; Assembly; Atomic layer deposition; Capacitance; Clamps; Compressive stress; Dielectric constant; Dielectric materials; Packaging; Plasma materials processing; Thermal stresses;

fLanguage

English

Publisher

ieee

Conference_Titel

Interconnect Technology Conference, 2003. Proceedings of the IEEE 2003 International

Print_ISBN

0-7803-7797-4

Type

conf

DOI

10.1109/IITC.2003.1219699

Filename

1219699