• DocumentCode
    1844126
  • Title

    Dual damascene patterning of polymer interlayer dielectrics

  • Author

    Hussein, Makarem ; Brain, Ruth ; Turkot, Robert ; Leu, Jihpemg ; Singh, Vivek ; Sivakumar, Sam

  • Author_Institution
    Logic Technol. Dev., Intel Corp., Hillsboro, OR, USA
  • fYear
    2003
  • fDate
    2-4 June 2003
  • Firstpage
    33
  • Lastpage
    35
  • Abstract
    We unveil an innovative and manufacturable process technique to pattern dual damascene structures in polymer interlayer dielectric (ILD) without the need for either a permanent hardmask or an embedded etch stop (ES) layer. We introduce a sacrificial hardmask (SAM) and a sacrificial via fill (SAVIL) material to enable the patterning process. Since the hardmask is sacrificial, it is removed at the end of the patterning process without compromising the overall dielectric value of the ILD. The utilization of the SAVIL material provided the trench lithography step with a hole-free, and planar substrate. We demonstrate patterning of dual damascene structures using SAM/SAVIL in a via-first integration scheme through a comparative patterning performance between the SAM/SAVIL-assisted dual damascene patterning and the dual hardmask approach used most in the industry.
  • Keywords
    dielectric materials; lithography; masks; polymer films; dual damascene patterning; embedded etch stop; first integration; manufacturable process; pattern dual damascene structures; permanent hardmask; planar substrate; polymer interlayer dielectrics; sacrificial hardmask; trench lithography; Copper; Dielectric constant; Dielectric materials; Etching; High K dielectric materials; Lithography; Logic; Manufacturing processes; Polymers; Simultaneous localization and mapping;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Interconnect Technology Conference, 2003. Proceedings of the IEEE 2003 International
  • Print_ISBN
    0-7803-7797-4
  • Type

    conf

  • DOI
    10.1109/IITC.2003.1219704
  • Filename
    1219704