• DocumentCode
    1844162
  • Title

    Quantitative characterization and process optimization of low-temperature bonded copper interconnects for 3-D integrated circuits

  • Author

    Tadepalli, Rajappa ; Thompson, Carl V.

  • Author_Institution
    Dept. of Mater. Sci. & Eng., Massachusetts Inst. of Technol., Cambridge, MA, USA
  • fYear
    2003
  • fDate
    2-4 June 2003
  • Firstpage
    36
  • Lastpage
    38
  • Abstract
    Three-dimensional (3-D) integrated circuits can be fabricated by bonding previously-processed device layers using metal-metal bonds that also serve as layer-to-layer interconnects. Bonded copper interconnect test structures were created by thermocompression bonding, and the bond toughness was measured using a four-point bend test. The effects of bonding temperature, chamber ambient and copper thickness on bond quality were evaluated to optimize the bonding process. A new copper surface cleaning method using glacial acetic acid was employed to obtain high toughness bonds(∼17 J/m2) at low bonding temperatures (<300°C).
  • Keywords
    copper; integrated circuit interconnections; lead bonding; surface cleaning; tape automated bonding; 3D integrated circuits; Cu; bond quality; bond toughness; bonding temperature; chamber ambient; copper surface cleaning method; four point bend test; glacial acetic acid; layer-layer interconnects; low temperature bonded copper interconnects; metal-metal bonds; thermocompression bonding; Bonding processes; Circuit testing; Copper; Integrated circuit interconnections; Integrated circuit technology; Materials science and technology; Surface cleaning; Temperature; Three-dimensional integrated circuits; Wafer bonding;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Interconnect Technology Conference, 2003. Proceedings of the IEEE 2003 International
  • Print_ISBN
    0-7803-7797-4
  • Type

    conf

  • DOI
    10.1109/IITC.2003.1219705
  • Filename
    1219705