CMOS implementation of a current conveyor-based field-programmable analog array

Author

Gaudet, Vincent C. ; Gulak, P. Glenn

Author_Institution

Dept. of Electr. & Comput. Eng., Toronto Univ., Ont., Canada

Volume

2

fYear

1997

fDate

2-5 Nov. 1997

Firstpage

1156

Abstract

To date, all published CMOS field-programmable analog array (FPAA) designs have operated under 1 MHz bandwidths. This paper develops circuit methods allowing the development of a CMOS FPAA operating at greater than 1 MHz frequencies. For this purpose the second-generation current conveyor (CCII) is used. IC test results of a 0.8 /spl mu/m CMOS chip containing four configurable analog blocks (CABs) based on the CCII, as well as an interconnection network based on transmission gates, are presented. The rest results show that bandwidths exceed 10 MHz. The four CABs and interconnect occupy a core area of 1551.8/spl times/74.1 /spl mu/m/sup 2/.

Keywords

CMOS analogue integrated circuits; current conveyors; integrated circuit interconnections; 0.8 micron; 10 MHz; CCII; CMOS implementation; FPAA; IC test results; configurable analog blocks; field-programmable analog array; interconnection network; second-generation current conveyor; transmission gates; Analog integrated circuits; Bandwidth; CMOS analog integrated circuits; CMOS integrated circuits; Circuit testing; Field programmable analog arrays; Frequency; Integrated circuit interconnections; Integrated circuit testing; Multiprocessor interconnection networks;

fLanguage

English

Publisher

ieee

Conference_Titel

Signals, Systems & Computers, 1997. Conference Record of the Thirty-First Asilomar Conference on

Conference_Location

Pacific Grove, CA, USA

ISSN

1058-6393

Print_ISBN

0-8186-8316-3

Type

conf

DOI

10.1109/ACSSC.1997.679086

Filename

679086