DocumentCode :
1844366
Title :
Arithmetic arrays using cellular neural networks
Author :
Sadeghi-Emamchaie, Saeid ; Jullien, G.A. ; Miller, W.C.
Author_Institution :
VLSI Res. Group, Windsor Univ., Ont., Canada
Volume :
2
fYear :
1997
fDate :
2-5 Nov. 1997
Firstpage :
1192
Abstract :
This paper discusses techniques for using locally connected analog cellular neural networks (CNNs) to implement arithmetic arrays. These arrays are targeted at low speed low-noise applications where continuous power/speed trade-offs and lower slew rate during transitions are potential advantages. Specifically, we demonstrate that a CNN array using a simple nonlinear feedback template, with hysteresis, for each node, can perform arbitrary length binary addition with good performance in terms of stability and robustness. The processing speed can be controlled by changing the self-feedback value of the templates. We also propose a method for using the adder in binary multiplication.
Keywords :
CMOS logic circuits; adders; cellular arrays; circuit feedback; digital arithmetic; neural chips; 0.5 micron; MOSIS CMOS technology; arithmetic arrays; binary addition; binary multiplication; continuous power/speed trade-offs; hysteresis; locally connected analog cellular neural networks; low speed applications; low-noise applications; nonlinear feedback template; performance; processing speed; robustness; self-feedback; slew rate; stability; Cellular neural networks; Digital arithmetic; Digital signal processing; Equations; Large-scale systems; Neurofeedback; Robust stability; State feedback; Very large scale integration; Voltage;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Signals, Systems & Computers, 1997. Conference Record of the Thirty-First Asilomar Conference on
Conference_Location :
Pacific Grove, CA, USA
ISSN :
1058-6393
Print_ISBN :
0-8186-8316-3
Type :
conf
DOI :
10.1109/ACSSC.1997.679093
Filename :
679093
Link To Document :
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