Non-traditional irregular interconnects for massive scale SoC

By using self-assembling fabrication techniques at the cellular, molecular, or atomic scale, it is nowadays possible to create functional assemblies in a mainly bottom-up way that involve massive numbers of interconnected components. However, such assemblies are often highly irregular, unreliable, and heterogeneous. A grand challenge for future and emerging electronics is thus to reliably and efficiently compute and communicate in such systems. The goal of this paper is to illustrate why non-traditional network-on-chip paradigms are promising for massive scale systems and what the limits are. We have previously shown that certain irregular 3D assemblies and interconnects have major advantages over regular 2D and 3D mesh fabrics in terms of latency, throughput, scalability, and the robustness against simple link failures. We present these results from a complex network perspective and look into the scaling properties of different interconnect topologies and routing algorithms in an abstract framework. We argue that only small-world topologies will scale up to massive scale systems. The long term goal in using irregular, fabrication-friendly, and non-traditional interconnects is to eventually be able to cheaply and easily assemble massive scale computing devices that are able to solve specific large- scale problems competitively with traditional top-down fabricated silicon technology.