Title :
Reliability improvement of Cu interconnects by additional anneal between Cu CMP and barrier CMP
Author :
Harada, T. ; Kobayashi, K. ; Takahashi, M. ; Nii, K. ; Ikeda, A. ; Ueda, T. ; Yabu, T.
Author_Institution :
ULSI Process Technol. Dev. Center, Matsushita Electr. Ind. Co. Ltd., Kyoto, Japan
Abstract :
The new technology which improves the reliability of Cu interconnects has been developed. In this technology, an anneal is carried out after a Cu CMP, followed by a barrier CMP and a p-SiN deposition. As a result, electromigration (EM) lifetime and stress-induced voiding (SIV) resistance have been improved drastically without the degradation of device performance and yield. Structural analyses suggest that the reliability improvement is realized by the reduction of tensile stress due to the stabilization of the Cu films and the minimization of the contact area of p-SiN/Cu interface due to the surface smoothing.
Keywords :
annealing; chemical mechanical polishing; copper; electromigration; grain size; integrated circuit interconnections; integrated circuit reliability; internal stresses; metallic thin films; semiconductor materials; semiconductor thin films; silicon compounds; surface morphology; Cu CMP; Cu films; Cu interconnects; SiN deposition; SiN-Cu; SiN/Cu interface; annealing; barrier CMP; electromigration; reliability; stress-induced voiding; structural analyses; surface smoothing; tensile stress; Degradation; Electrical resistance measurement; Electromigration; Integrated circuit interconnections; Minimization; Reliability engineering; Simulated annealing; Temperature; Tensile stress; Testing;
Conference_Titel :
Interconnect Technology Conference, 2003. Proceedings of the IEEE 2003 International
Print_ISBN :
0-7803-7797-4
DOI :
10.1109/IITC.2003.1219722
