Title :
Porous dielectric dual damascene patterning issues for 65 nm node: can architecture bring a solution?
Author :
Assous, M. ; Simon, J. ; Broussous, L. ; Bourlot, C. ; Fayolle, M. ; Louveau, O. ; Roman, A. ; Tabouret, E. ; Feldis, H. ; Louis, D. ; Torres, J.
Author_Institution :
CEA Grenoble-LETI, Grenoble, France
Abstract :
A dual hard mask, dual damascene architecture was developed to circumvent integration problems brought by porous ULK dielectric use. It was demonstrated that a via first strategy with adequately defined hard masks can improve patterning conditions.
Keywords :
dielectric materials; masks; photoresists; porous materials; silicon compounds; wide band gap semiconductors; Porous dielectric dual damascene patterning; SiC; circumvent integration; dual damascene architecture; dual hard mask; strategy; Ash; Automotive materials; Cleaning; Dielectric materials; Lithography; Material storage; Plasma applications; Plasma chemistry; Resists; Testing;
Conference_Titel :
Interconnect Technology Conference, 2003. Proceedings of the IEEE 2003 International
Print_ISBN :
0-7803-7797-4
DOI :
10.1109/IITC.2003.1219723
