Title :
An ADD-based algorithm for shortest path back-tracing of large graphs
Author :
Bahar, R. Iris ; Hachtel, G.D. ; Pardo, Abelardo ; Poncino, Massimo ; Somenzi, Fabio
Author_Institution :
Dept. of Electr. & Comput. Eng., Colorado Univ., Boulder, CO
Abstract :
Symbolic computation techniques play a fundamental role in logic synthesis and formal hardware verification algorithms. Recently, Algebraic Decision Diagrams, i.e., BDDs with a set of constant values different to the set {0,1}, have been used to solve general purpose problems, such as matrix multiplication, shortest path calculation, and solution of linear systems, as well as logic synthesis and formal verification problems, such as timing analysis, probabilistic analysis of finite state machines, and state space decomposition for approximate finite state machine traversal. ADD-based procedures for single-source and all-pairs shortest path weight calculation have appeared to be very effective for the manipulation of large graphs (over 1027 vertices and 1036 edges). However, for those procedures to be applicable to real problems, for example flow network problems, computing only shortest path weights is not enough; what it is needed is an algorithm that, given the weight of a shortest path between two vertices of a graph, actually determines the sequence of vertices belonging to the shortest path. This paper proposes a symbolic algorithm to execute shortest path back-tracing which exploits the compactness of the ADD data structure to handle large graphs
Keywords :
data structures; directed graphs; finite state machines; formal verification; logic CAD; symbol manipulation; ADD data structure; ADD-based algorithm; Algebraic Decision Diagrams; finite state machines; flow network problems; formal verification; logic synthesis; probabilistic analysis; shortest path back-tracing; state space decomposition; symbolic algorithm; symbolic computation techniques; Automata; Boolean functions; Data structures; Formal verification; Hardware; Linear systems; Logic functions; Matrix decomposition; Probabilistic logic; Timing;
Conference_Titel :
VLSI, 1994. Design Automation of High Performance VLSI Systems. GLSV '94, Proceedings., Fourth Great Lakes Symposium on
Conference_Location :
Notre Dame, IN
Print_ISBN :
0-8186-5610-7
DOI :
10.1109/GLSV.1994.289960