Title :
An improved algorithm for the generalized min-cut partitioning problem
Author :
Tragoudas, Spyros
Author_Institution :
Dept. of Comput. Sci., Southern Illinois Univ., Carbondale, IL, USA
Abstract :
We consider the generalization of the min-cut partitioning problem in which the nodes of a circuit C are to be mapped to the vertices of a graph G, and the cost function to be minimized is the cost of associating the nets of C with the edges of G. Vijayan (see IEEE Trans. on Computers, vol. 40, no. 3, 1991) recently presented an iterative improvement heuristic for the case when G is a tree T. Let P be the number of pins, t be the number of nodes of T, and d be the maximum number of cells on a net of C. The running time of a pass of the heuristic given in Vijayan´s paper is O(P·t3). For a graph G, this approach requires O(P·t4) time per pass. We present a heuristic for this particular problem which guarantees exactly the same partitions in time O(P·t min{d,t}) per pass, for any graph G. The problem finds important applications in a variety of situations that arise in VLSI physical design, and in distributed systems
Keywords :
VLSI; circuit layout CAD; graph theory; VLSI physical design; cost function; distributed systems; generalized min-cut partitioning problem; iterative improvement heuristic; Circuits; Computer science; Cost function; Partitioning algorithms; Pins; Tree graphs; Very large scale integration; Virtual colonoscopy;
Conference_Titel :
VLSI, 1994. Design Automation of High Performance VLSI Systems. GLSV '94, Proceedings., Fourth Great Lakes Symposium on
Conference_Location :
Notre Dame, IN
Print_ISBN :
0-8186-5610-7
DOI :
10.1109/GLSV.1994.289961