Title :
Area, performance, and sensitizable paths [logic design]
Author :
Kapoor, Bhanu ; Nair, V.S.S.
Author_Institution :
Integrated Syst. Lab., Texas Instrum. Inc., Dallas, TX, USA
Abstract :
In this paper, we investigate the problem of modifying a synthesized circuit to improve its path sensitizability. It is shown that a large number of paths, which cannot be sensitized using single-transition tests, are redundant paths and they can be removed by appropriate modification of the circuit. The effect of these modifications on area and performance of the circuit has been analyzed. For the paths which are neither redundant nor sensitizable using single-transition tests, it is shown that they can be sensitized using multiple-transition tests. Results obtained on some common benchmark examples suggest the validity and viability of this approach
Keywords :
combinatorial circuits; design for testability; logic design; redundancy; circuit performance; circuits area; logic design; multiple-transition tests; path sensitizability; redundant paths; sensitizable paths; single-transition tests; synthesized circuit; Benchmark testing; Circuit faults; Circuit synthesis; Circuit testing; Combinational circuits; Computer science; Delay; Logic design; Robustness; Terminology;
Conference_Titel :
VLSI, 1994. Design Automation of High Performance VLSI Systems. GLSV '94, Proceedings., Fourth Great Lakes Symposium on
Conference_Location :
Notre Dame, IN
Print_ISBN :
0-8186-5610-7
DOI :
10.1109/GLSV.1994.289965
