Retiming algorithms with application to VLSI testability

A very popular and established methodology for testing complex sequential circuits is to break the cyclic structure of the circuit by incorporating a minimum number of flip-flops into a partial scan register. The circuit can then be tested by applying sequences of test patterns or using techniques for testing combinational logic. In the former case, it is very important to minimize the sequential depth, i.e. the maximum number of flip-flops on any path from the inputs to the outputs. In the latter case, it is also necessary to balance the circuit, so that all paths between any pair of nodes have the same number of flip-flops. In this paper, we address the above goals using the sequential logic synthesis concept of retiming. We present polynomial-time algorithms that solve optimally the following problems: (i) minimization of the sequential depth of the circuit; (ii) minimization of the number of flip-flops in the circuit so that the sequential depth and the clock period are less than prescribed bounds; and (iii) minimization of the number of flip-flops that need to be inserted in the circuit so that it becomes balanced. These algorithms extend the areas where retiming can be successfully applied