DocumentCode
1845155
Title
Design of a 54-bit adder using a modified Manchester carry chain
Author
Hashemian, Reza
Author_Institution
Dept. of Electr. Eng., Northern Illinois Univ., DeKalb, IL, USA
fYear
1994
fDate
4-5 Mar 1994
Firstpage
204
Lastpage
207
Abstract
A new design based on a modified Manchester carry adder is presented. The modification provides bypass routes for the carry to propagate when the carry path through the chain is long. The computational speed received is quite high for high density codes. Much similar to carry look-ahead adders the bypass routes are activated through a series of group carries, in different levels, generated by a NAND/NOR tree network. It is shown that for a 54-bit adder the longest delay through the carry chain is equivalent to the delay through only 11 pass transistors. The algorithm is implemented for the design of a 54-bit adder using CMOS technology
Keywords
CMOS integrated circuits; adders; carry logic; integrated logic circuits; logic design; CMOS technology; Manchester carry adder; NAND/NOR tree network; bypass routes; computational speed; delay; group carries; modified Manchester carry chain; Added delay; Adders; Algorithm design and analysis; CMOS technology; Circuits; Clocks; Monitoring; Propagation delay; Signal generators; Silicon;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI, 1994. Design Automation of High Performance VLSI Systems. GLSV '94, Proceedings., Fourth Great Lakes Symposium on
Conference_Location
Notre Dame, IN
Print_ISBN
0-8186-5610-7
Type
conf
DOI
10.1109/GLSV.1994.289968
Filename
289968
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