Title :
An efficient multiprocessor implementation scheme for real-time DSP algorithms
Author :
Hu, Yu Hen ; Wang, Duen-Jeng
Author_Institution :
Dept. of Elect. and Comput. Eng., Wisconsin Univ., WI, USA
Abstract :
An algorithm to derive minimum-processor implementation for real-time DSP algorithms is proposed. In order to make the number of possible schedules finite and to assure the optimal schedule within the search space, the authors define a novel notion of cutoff time. All the possible schedules can find an equivalent schedule that finishes before cutoff time. Next, they apply all efficient heuristic periodic scheduling and fully static allocation algorithms derived from two generic problem solving heuristics developed in a branch of artificial intelligence research called planning. Extensive benchmarks have been tested and the results are most encouraging
Keywords :
VLSI; digital signal processing chips; heuristic programming; parallel architectures; planning (artificial intelligence); VLSI; artificial intelligence; cutoff time; fine-grain parallelism; fully static allocation algorithms; generic problem solving heuristics; heuristic periodic scheduling; minimum-processor implementation; multiprocessor implementation scheme; optimal schedule; planning; real-time DSP algorithms; search space; Clocks; Delay; Digital signal processing; Digital signal processing chips; Iterative algorithms; Optimal scheduling; Processor scheduling; Sampling methods; Scheduling algorithm; Signal processing algorithms;
Conference_Titel :
VLSI, 1994. Design Automation of High Performance VLSI Systems. GLSV '94, Proceedings., Fourth Great Lakes Symposium on
Conference_Location :
Notre Dame, IN
Print_ISBN :
0-8186-5610-7
DOI :
10.1109/GLSV.1994.289971