Novel dual damascene patterning technology for ultra low-κ dielectrics

In this article, we present a novel via-sealing-architecture (VISA) dual damascene patterning technology, featuring with immunity from PR poisoning and ash-induced degradation of porous low-k dielectrics, and planar surface topology for both via and trench lithography. Its electrical performance is demonstrated by integrating Cu and porous organosilicate glass (OSG), κ=2.2, with 90 nm design rule and 193 nm lithography on the 300 mm wafer. The new architecture, which consists of depositing hard-mask dielectrics over the etched hole to form a sealed structure, enables this patterning technology extending to 65 nm generation and below without influenced by low-k materials and lithography technology.