Title :
Novel dissoluble hardmask for damage-less Cu/low-k interconnect fabrication
Author :
Furusawa, Takeshi ; Machida, Shuntaro ; Ryuzaki, Daisuke ; Sameshima, Kenji ; Ishida, Takeshi ; Ishikawa, Kensuke ; Miura, Noriko ; Konishi, Nobuhiro ; Saito, Tatsuyuki ; Yamaguchi, Hizuru
Author_Institution :
Semicond. & Integrated Circuits, Hitachi Ltd., Tokyo, Japan
Abstract :
A Cu/low-k dual-damascene process using a novel dissoluble hardmask material, AlO, is developed to suppress ashing-damage to porous/nonporous low-k SiOC. In this process, ArF-resist patterns are firstly transferred to a very thin, typically 30-nm-thick, AlO hardmask layer. After removing the resist, SiOC is patterned using the hardmask. The hardmask remaining after the etching is spontaneously removed during post-etch wet-cleaning. The line-to-line capacitance of 280-nm-pitch, 4-level interconnects using this process is reduced by 10% from that using a conventional resist-mask process.
Keywords :
aluminium compounds; capacitance; copper; dielectric materials; integrated circuit interconnections; lithography; masks; porous materials; resists; silicon compounds; sputter deposition; sputter etching; surface cleaning; 280 nm; 30 nm; AlO; AlO hardmask layer; ArF-resist patterns; Cu-SiOC; ashing-damage; capacitance; damageless Cu/low-k interconnect fabrication; dissoluble hardmask; etching; patterning; porous/nonporous low-k SiOC; post-etch wet cleaning; resist-mask process; Cleaning; Dielectric materials; Dry etching; Fabrication; Integrated circuit interconnections; Plasma applications; Plasma materials processing; Resists; Sputter etching; Wet etching;
Conference_Titel :
Interconnect Technology Conference, 2003. Proceedings of the IEEE 2003 International
Print_ISBN :
0-7803-7797-4
DOI :
10.1109/IITC.2003.1219752
