High-performance ASIC implementations of the 128-bit block cipher CLEFIA

Author

Sugawara, Takeshi ; Homma, Naofumi ; Aoki, Takafumi ; Satoh, Akashi

Author_Institution

Grad. Sch. of Inf. Sci., Tohoku Univ., Sendai

fYear

2008

fDate

18-21 May 2008

Firstpage

2925

Lastpage

2928

Abstract

In the present paper, we introduce high-performance hardware architectures for the 128-bit block cipher CLEFIA and evaluate their ASIC performances in comparison with the ISO/IEC 18033-3 standard block ciphers (AES, Camellia, SEED, CAST-128, MISTY1, and TDEA). We designed five types of hardware architectures for CLEFIA, combining two loop structures and three F-functions. These designs were synthesized with a 90-nm CMOS standard cell library, and size and speed performances were evaluated. The highest hardware efficiency (defined as throughput/gates) obtained was 400.96 Kbps/gates, which is 1.5 times higher than previously achieved efficiencies.

Keywords

CMOS integrated circuits; application specific integrated circuits; integrated circuit design; AES; ASIC; CAST-128; CLEFIA; CMOS standard cell library; Camellia; F-functions; ISO/IEC 18033-3 standard block ciphers; MISTY1; SEED; TDEA; hardware architectures; size 90 nm; word length 128 bit; Application specific integrated circuits; CMOS technology; Galois fields; Hardware; IEC standards; ISO standards; Information security; Libraries; Performance evaluation; Throughput;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2008. ISCAS 2008. IEEE International Symposium on

Conference_Location

Seattle, WA

Print_ISBN

978-1-4244-1683-7

Electronic_ISBN

978-1-4244-1684-4

Type

conf

DOI

10.1109/ISCAS.2008.4542070

Filename

4542070