Design of a package for a high-speed processor made with yield-limited technology

Author

Garg, A. ; Loy, J. ; Greub, H. ; McDonald, J.F.

Author_Institution

Center for Integrated Electron., Rensselaer Polytech. Inst., Troy, NY, USA

fYear

1994

fDate

4-5 Mar 1994

Firstpage

110

Lastpage

113

Abstract

The design of an advanced high density thin film multichip module (MCM) for a 1-ns cycle time Fast Reduced Instruction Set Computer (F-RISC/G) is described. The processor has been implemented with GaAs/AlGaAs heterojunction bipolar transistor (HBT) technology from Rockwell International. The F-RISC/G package pushes the state of the art to satisfy electrical, thermal and thermomechanical constraints to take advantage of this high speed circuit technology. A unique approach is developed to link the electrical and thermomechanical design environments using a common database

Keywords

bipolar integrated circuits; emitter-coupled logic; microprocessor chips; multichip modules; reduced instruction set computing; 1 ns; F-RISC/G; Fast Reduced Instruction Set Computer; electrical constraints; heterojunction bipolar transistor technology; high density thin film multichip module; high-speed processor; thermal constraints; thermomechanical constraints; yield-limited technology; Crosstalk; Gallium arsenide; Geometry; Heterojunction bipolar transistors; Integrated circuit interconnections; Logic; Military computing; Packaging; Thermal stresses; Wires;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI, 1994. Design Automation of High Performance VLSI Systems. GLSV '94, Proceedings., Fourth Great Lakes Symposium on

Conference_Location

Notre Dame, IN

Print_ISBN

0-8186-5610-7

Type

conf

DOI

10.1109/GLSV.1994.289985

Filename

289985