DocumentCode :
1845582
Title :
Porous low k pore sealing process study for 65 nm and below technologies
Author :
Mourier, T. ; Jousseaume, V. ; Fusalba, F. ; Lecornec, Ch ; Maury, P. ; Passemard, G. ; Haumesser, PH ; Maîtrejean, S. ; Cordeau, M. ; Pantel, R. ; Pierre, F. ; Fayolle, M. ; Feldis, H.
Author_Institution :
DRT, CEA, Grenoble, France
fYear :
2003
fDate :
2-4 June 2003
Firstpage :
245
Lastpage :
247
Abstract :
65 nm and below technologies will require a combination of porous ultra low k dielectric and copper metallization. Feature size may need the use of conformal metallic barrier deposition methods like CVD or ALD. One of the key issues for integration of such materials come from the tendency for precursor to diffuse through the porous structure degrading effective k value. Various pore sealing methodologies were already investigated and reported. In this paper, we describe a process based on the deposition of a thin dielectric liner that allows sealing of surface pores without impacting too much dielectric properties of ULK material. Physico-chemical analysis were carried out and confirmed by electrical measurements.
Keywords :
CVD coatings; copper; dielectric materials; dielectric thin films; integrated circuit metallisation; permittivity; porous materials; ALD; CVD; Cu; copper metallization; dielectric properties; electrical measurements; metallic barrier deposition; physico-chemical analysis; pore sealing process; porous structure; porous ultra low k dielectric; surface pores; Conducting materials; Copper; Dielectric materials; Inorganic materials; Metallization; Plasma density; Sealing materials; Seals; Surface treatment; Tin;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Interconnect Technology Conference, 2003. Proceedings of the IEEE 2003 International
Print_ISBN :
0-7803-7797-4
Type :
conf
DOI :
10.1109/IITC.2003.1219766
Filename :
1219766
Link To Document :
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