Process variations aware robust on-chip bus architecture synthesis for MPSoCs

Two major trends can be observed in a modern system-on- chip design: first a growing trend in system complexity, which results in a sharp increase of communication traffic on the on-chip communication bus architectures. The second in technology scaling indicates that the wires are getting thinner and results in an increment of wire delay and power consumption. These, in turn, result in the degradation of both device reliability and system performance. As the process technology is scaled down, the effects of process variation are becoming significant on system performance. In order to incorporate the combined effects process variations on the performance of on-chip bus architecture, this work proposes a technique to synthesize an energy conscious robust on- chip bus architecture. The proposed model simultaneously performs on- chip bus synthesis and voltage scaling under both data size and process parameters variations. The problem is relaxed to a nonlinear optimization model, which synthesizes an energy conscious optimal bus widths and the number of buses considering worst case data traffic and process variations. The experimental results show that applying voltage scaling during the synthesis of on-chip bus effectively reduces the dynamic power consumption, leakage power consumption, and mitigates the effects of process variations.