An assessment of the behavior of compact thermal models of electronic packages in a printed circuit board level environment

This paper outlines research aimed at testing compact thermal models in various board level environments. Results for two generic package types are presented: CPGA and a BGA. A validated fully detailed finite element model and a compact thermal model (CTM) were generated for each. A smeared finite element model of the JEDEC standard thermal test PCBs for each package was built. The boards were modeled assuming both isotropic and anisotropic effective (smeared) thermal conductivities for the PCB. The CTM and fully detailed model (FDM) for each package were "mounted" to its respective test boards. Finite element analysis was performed for each board and package system for a set of five convective boundary sets chosen to test the limits of the models. Runs were also conducted in which heated components were placed with varied proximity to the package model on a larger test board. Comparisons were made of the temperatures predicted by the package FDM/board models and the CTM/board model. The CTM models were found in general to predict junction temperatures to within 5% of the results found using the FDM of the chip packages/board in realistic cooling scenarios.