A 600 MHz 2D-DCT processor for MPEG applications

In this paper we present the design of a 2D discrete cosine transform (2D-DCT) processor and its implementation using 0.6 /spl mu/m GaAs technology. The architecture of the processor, that resembles an FCT-MMM (fast cosine transform-matrix matrix multiplication) architecture, was development using distributed arithmetic (DA) in order to reduce the area required. The processor has about 50k transistors and occupies an area of 31.8 mm/sup 2/. It is able to process 400 Mpixels per second and at a clock frequency of 600 MHz, which is far beyond the requirements for real time high definition moving pictures in the MPEG-2 standard. Special consideration is given to the implementation of a transposition RAM which constitutes the bottleneck of the algorithm. A 64 word/spl times/12 bit, 1 ns access time transposition RAM was developed using a new dynamic RAM cell.