Title :
Floorplan optimization on multiprocessors
Author :
Arvindam, S. ; Kumar, Vipin ; Rao, V. Nageshwara
Author_Institution :
Texas Univ., Austin, TX, USA
Abstract :
A parallel formulation of a branch-and-bound algorithm for floorplan optimization in VLSI design is given. Implementation details and performance analyses of the authors´ formulation are presented. This implementation was done on a 128-node Symult s2010 multicomputer, as well as on a network of 16 SUN workstations. In the experiments with realistic problems, linear speedups on both machine configurations were obtained. Previous analyses of a similar parallel algorithm suggest that linear speedup can be obtained even on very large computers (>1000 processors) on practical instances of this problem
Keywords :
VLSI; circuit layout CAD; engineering workstations; multiprocessing systems; parallel algorithms; 128-node Symult s2010 multicomputer; SUN workstations; VLSI; branch-and-bound algorithm; floorplan optimization; linear speedups; machine configurations; multiprocessors; parallel formulation; Algorithm design and analysis; Computer networks; Concurrent computing; Costs; Design optimization; Parallel algorithms; Performance analysis; Sun; Very large scale integration; Workstations;
Conference_Titel :
Computer Design: VLSI in Computers and Processors, 1989. ICCD '89. Proceedings., 1989 IEEE International Conference on
Conference_Location :
Cambridge, MA
Print_ISBN :
0-8186-1971-6
DOI :
10.1109/ICCD.1989.63338
