Title :
A passive filter aided timing recovery scheme
Author :
Musa, Faisal A. ; Carusone, Anthony Chan
Author_Institution :
Edward S. Rogers Sr. Dept. of Electr. & Comput. Eng., Univ. of Toronto, Toronto, ON
Abstract :
This paper presents a passive Alter for the front end of a high speed serial link receiver to aid timing recovery. The Alter provides simultaneous lowpass and highpass transfer characteristics to generate the data and its slope respectively. Slope detection is demonstrated at 10-Gb/s. As a proof of concept, the Alter was used to extract a 2-GHz clock from a 2-Gb/s 231- 1 random data sequence based on a modified minimum mean squared error (MMSE) criterion. The circuit is fabricated in a 0.18 mum CMOS process and consumes 21.6 mW from a 1.8 V supply.
Keywords :
CMOS integrated circuits; UHF filters; high-pass filters; least mean squares methods; low-pass filters; passive filters; receivers; synchronisation; CMOS process; aid timing recovery scheme; bit rate 10 Gbit/s; bit rate 2 Gbit/s; frequency 2 GHz; high speed serial link receiver; highpass filter; lowpass filter; modified minimum mean squared error criterion; passive filter; power 21.6 mW; size 0.18 mum; slope detection; voltage 1.8 V; Active filters; Circuits; Clocks; Detectors; Educational institutions; Jitter; Passive filters; Sampling methods; Strontium; Timing;
Conference_Titel :
Circuits and Systems, 2008. ISCAS 2008. IEEE International Symposium on
Conference_Location :
Seattle, WA
Print_ISBN :
978-1-4244-1683-7
Electronic_ISBN :
978-1-4244-1684-4
DOI :
10.1109/ISCAS.2008.4542105
