DocumentCode
1845957
Title
Integration Of Clock Skew And Register Delays Into A Retiming Algorithm
Author
Soyata, Tolga ; Friedman, Eby G.
Author_Institution
University of Rochester
fYear
1993
fDate
3-6 May 1993
Firstpage
1483
Lastpage
1486
Keywords
Circuit synthesis; Clocks; Combinational circuits; Delay estimation; Frequency estimation; Frequency synchronization; Latches; Pipeline processing; Pulse circuits; Registers;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1993., ISCAS '93, 1993 IEEE International Symposium on
Conference_Location
IEEE
Print_ISBN
0-7803-1281-3
Type
conf
Filename
692938
Link To Document