Reducing Power Consumption of Multiplier via Narrow-width Operand Detecting

Power consumption is a critical issue in functional unit design. Focusing on the condition of the positive narrow-width operands, this paper presents a low-power multiplier. Compared with the baseline multiplier, an additional width detector is employed in front of the operand register in the proposed multiplier. With the width information supplied by the width detector, computation modules in the multiplier could avoid unnecessary activities of the computation circuits when narrow-width operand appears. Experimental results show the multiplier could achieve an average of 21% power consumption when calculating the 32-bit operands with random valid bits, with 6.9% area overhead. The proposed design incurs 2.7% delay increase in the stage where the multiplier locates and the width detector also enlarges delay of the formal stage by 0.68ns in 180nm technology.