Title :
Optimizing cyclic data-flow graphs via associativity
Author :
Chao, Liang-Fang
Author_Institution :
Dept. of Electr. Eng. & Comput. Eng., Iowa State Univ., Ames, IA, USA
Abstract :
An iterative or recursive algorithm, with interiteration precedence relations is represented by a cyclic data-flow graph (DFG), where nodes represented operations. Such a DFG has a lower bound on the schedule length, which is determined by the loops (cycles) in the cyclic DFG. Associativity of the operations can be applied to restructure a DFC while preserving the behavior of the given recursive algorithm. We propose a measure of criticalness on regions of a DFG in order to guide the application of associativity to effectively reduce the lower bound or schedule length. Experimental results show that the transformed dataflow graph gives the best known schedules even under resource constraints
Keywords :
VLSI; circuit layout CAD; graph theory; integrated logic circuits; iterative methods; logic CAD; scheduling; associativity; compiler design; cyclic data-flow graphs; high-level synthesis; interiteration precedence relations; iterative algorithm; lower bound; recursive algorithm; resource constraints; schedule length; Computer science; Delay effects; Flow graphs; Parallel processing; Petroleum; Pipeline processing; Processor scheduling; Program processors; Tree graphs;
Conference_Titel :
VLSI, 1994. Design Automation of High Performance VLSI Systems. GLSV '94, Proceedings., Fourth Great Lakes Symposium on
Conference_Location :
Notre Dame, IN
Print_ISBN :
0-8186-5610-7
DOI :
10.1109/GLSV.1994.290005