• DocumentCode
    1846034
  • Title

    Novel interpolation architecture for Low-Complexity Chase soft-decision decoding of Reed-Solomon codes

  • Author

    Zhu, Jiangli ; Zhang, Xinmiao ; Wang, Zhongfeng

  • Author_Institution
    Case Western Reserve Univ., Cleveland, OH
  • fYear
    2008
  • fDate
    18-21 May 2008
  • Firstpage
    3078
  • Lastpage
    3081
  • Abstract
    Algebraic soft-decision decoding (ASD) of Reed-Solomon (RS) codes can provide substantial coding gain with polynomial complexity. Among the ASD algorithms with practical multiplicity assignment schemes, the low-complexity chase (LCC) decoding can achieve similar or higher coding gain. Interpolation is a major step in ASD. Since the maximum multiplicity of the interpolation point is only one in LCC, the interpolation over each point has low complexity. However, 2n test vectors are involved in the LCC, and the interpolation needs to be carried out on each of them. In order to reduce the computational complexity of the overall interpolation, intermediate results can be stored and shared. Nevertheless, the storage requires large memory, which accounts for a significant portion of the overall hardware requirement of the interpolator. In this paper, we propose a novel interpolation procedure, in which the 2n test vectors are mapped to the vertices of a dimension-n hypercube and the vectors mapped to adjacent vertices have only one different entry. In addition, a backward interpolation is proposed to support the traversal from one vertex to its neighbors. Traveling through the entire hypercube, the interpolation over each test vector can be done one after another and the memory requirement is reduced by a factor of 2´7~1. Efficient architectures are also developed for the proposed interpolation procedure. With about the same latency and the same number of gates as in prior efforts, our architecture can reduce the memory size to 25% and the number of registers to 57% for a (255, 239) RS code with n = 3. The saving further increases with n.
  • Keywords
    Reed-Solomon codes; decoding; interpolation; Reed-Solomon codes; algebraic soft-decision decoding; interpolation architecture; low-complexity chase decoding; polynomial complexity; Computational complexity; Decoding; Delay; Hardware; Hypercubes; Interpolation; Reed-Solomon codes; Registers; Testing; Variable speed drives;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems, 2008. ISCAS 2008. IEEE International Symposium on
  • Conference_Location
    Seattle, WA
  • Print_ISBN
    978-1-4244-1683-7
  • Electronic_ISBN
    978-1-4244-1684-4
  • Type

    conf

  • DOI
    10.1109/ISCAS.2008.4542108
  • Filename
    4542108