A 600-Mb/s encoder and decoder for low-density parity-check convolutional codes

Author

Brandon, Tyler ; Koob, John C. ; van den Berg, L. ; Chen, Zhengang ; Alimohammad, Amirhossein ; Swamy, Ramkrishna ; Klaus, Jason ; Bates, Stephen ; Gaudet, Vincent C. ; Cockburn, Bruce F. ; Elliott, Duncan G.

Author_Institution

Dept. of Electr. & Comput. Eng., Univ. of Alberta, Edmonton, AB

fYear

2008

fDate

18-21 May 2008

Firstpage

3090

Lastpage

3093

Abstract

A 600-Mb/s rate-1/2 (128,3,6) LDPC convolutional code encoder and decoder was implemented in a 90-nm CMOS process. The encoder operates at 1.1 GHz and includes built-in all-phase termination. The decoder design maximizes throughput while minimizing the number of memory banks and delivering an information throughput of 1 bit per clock cycle. The size of the decoder controller is minimized by sharing it among an arbitrary number of decoder processors. The decoder dissipates 0.61 nJ of energy per decoded information bit at an SNR of 2.0 and a throughput of 600 Mb/s. An integrated test system enables accurate power measurements for various SNR settings.

Keywords

CMOS integrated circuits; convolutional codes; encoding; parity check codes; CMOS process; decoder; encoder; frequency 1.1 GHz; low-density parity-check convolutional code; size 90 nm; CMOS process; Clocks; Convolutional codes; Decoding; Energy consumption; Equations; Measurement; Parity check codes; Testing; Throughput;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2008. ISCAS 2008. IEEE International Symposium on

Conference_Location

Seattle, WA

Print_ISBN

978-1-4244-1683-7

Electronic_ISBN

978-1-4244-1684-4

Type

conf

DOI

10.1109/ISCAS.2008.4542111

Filename

4542111