Linear-enhanced V to I converters based on MOS resistive source degeneration

This paper describes the application of the quasi- floating gate technique to overcome the common mode sensitivity of the degeneration MOS resistors, which results in a significant linearity improvement and an enhanced CMRR. The proposed approach requires minimal additional hardware, does not require increased supply voltages or additional quiescent power dissipation and preserves the possibility of tuning the MOS resistor value through small gate voltage variations. Results from two different linearized MOS source degeneration schemes implemented in a 0.5 mum CMOS technology verify the feasibility of the presented solution.