Title :
Implementation of high-performance multi-structure digital down converter based on FPGA
Author :
Zhuo Zhi-hai ; Li Shan-ge ; Li Wen-guang ; Liu Ben-lu ; Zhang Ze-chao
Author_Institution :
Sch. of Inf. & Electron., Beijing Inst. of Technol., Beijing, China
Abstract :
Digital Down Conversion(DDC) is a key technology of Software Radio. Traditional implementations consume more resources and are difficult to achieve high Signal-to-Noise Ratio(SNR) gain. To solve this problem, an optimized filter structure of DDC for acquiring high SNR gain is presented. The effect of finite word length of filter coefficients and output rounding on the performance of DDC are investigated. In the Matlab and Xilinx ISEl0.1 simulation development environment, Virtex-5 XC5VLX110T FPGA chip is used to implement a variety of different filter structure DDC design, then some critical indices such as SNR gain and resource consumption of each scheme are compared. Experimental results show that the 1000 times decimation DDC of entire-FIR-filters structure meets all the performance requirements, whose SNR gain is up to 28.0515dB, which is substantially better than that of the conventional structure.
Keywords :
IIR filters; field programmable gate arrays; logic design; performance evaluation; software radio; DDC design; FIR filter structure; FPGA; Matlab simulation development environment; SNR gain; Virtex-5 XC5VLX110T FPGA chip; Xilinx ISE10.1 simulation development environment; high-performance multistructure digital down converter; optimized filter structure; performance requirements; resource consumption; signal-to-noise ratio; software radio; Digital Down Converter; FPGA; filter structure; finite word length effect;
Conference_Titel :
Signal Processing (ICSP), 2012 IEEE 11th International Conference on
Conference_Location :
Beijing
Print_ISBN :
978-1-4673-2196-9
DOI :
10.1109/ICoSP.2012.6491661
