• DocumentCode
    1846619
  • Title

    A Scheme of Test Pattern Generation Based on Reseeding of Segment-Fixing Counter

  • Author

    Chen, Tian ; Liang, Huaguo ; Zhang, Minsheng ; Wang, Wei

  • Author_Institution
    Sch. of Comput. & Inf., Hefei Univ. of Technol., Hefei
  • fYear
    2008
  • fDate
    18-21 Nov. 2008
  • Firstpage
    2272
  • Lastpage
    2277
  • Abstract
    This paper proposes a new BIST test pattern generation scheme based on random access scan architecture. In this scheme, segment-fixing strategy is used to BIST test pattern generator based on a counter, which can reduce the number of redundant test patterns, and improve the efficiency of test patterns generation. As random access scan mechanism is utilized in this scheme, only one scan cell needs to be updated when a new test pattern is fed to scan cells. Experimental results on ISCAS-89 benchmark show that the scheme can effectively reduce test data volume, test application time and test power consumption.
  • Keywords
    built-in self test; integrated circuit testing; storage management chips; BIST test pattern generation scheme; random access scan architecture; segment-fixing counter reseeding; test pattern generation; Automatic testing; Benchmark testing; Built-in self-test; Circuit testing; Computer architecture; Counting circuits; Decoding; Power dissipation; Tellurium; Test pattern generators; Segment fixing counter; random access scan; test pattern generation;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Young Computer Scientists, 2008. ICYCS 2008. The 9th International Conference for
  • Conference_Location
    Hunan
  • Print_ISBN
    978-0-7695-3398-8
  • Electronic_ISBN
    978-0-7695-3398-8
  • Type

    conf

  • DOI
    10.1109/ICYCS.2008.216
  • Filename
    4709326