DocumentCode :
184734
Title :
A compact neural core for digital implementation of the Neural Engineering Framework
Author :
Runchun Wang ; Hamilton, T.J. ; Tapson, J. ; van Schaik, A.
Author_Institution :
MARCS Inst., Univ. of Western Sydney, Sydney, NSW, Australia
fYear :
2014
fDate :
22-24 Oct. 2014
Firstpage :
548
Lastpage :
551
Abstract :
The Neural Engineering Framework (NEF) is a tool that is capable of synthesising large-scale cognitive systems from subnetworks; and it has been used to construct SPAUN, which is the first brain model capable of performing cognitive tasks. It has been implemented on computers using high-level programming languages. However the software model runs much slower than real time, and therefore is not capable of performing for applications that need real-time control, such as interactive robotic systems. Here we present a compact neural core for digital implementation of the NEF on Field Programmable Gate Arrays (FPGAs) in real time. The proposed digital neural core consists of 64 neurons that are instantiated by a single physical neuron using a time-multiplexing approach. As NEF intrinsically uses a spike rate-encoding paradigm, rather than implementing spiking neurons and then measuring their firing rates, we chose to implement NEF with neurons that compute their firing rate directly. The neuron is efficiently implemented using a 9-bit fixed-point multiplier without the requirement of memory, the bandwidth of memory being the bottleneck for the time-multiplexing approach. The neural core uses only a fraction of the hardware resources in a commercial-off-the-shelf FPGA (even an entry level one) and can be easily programmed for different mathematical computations. Multiple cores can easily be combined to build real-time large-scale cognitive neural networks using the Neural Engineering Framework.
Keywords :
bioelectric potentials; brain models; cellular biophysics; cognition; field programmable gate arrays; multiplexing; neural nets; brain model; digital neural core; field programmable gate arrays; high-level programming languages; interactive robotic systems; mathematical computations; memory bandwidth; neural engineering framework; neuron firing rate computation; nine-bit fixed-point multiplier; real-time large-scale cognitive neural networks; software model; spike rate-encoding paradigm; time-multiplexing approach; Biological neural networks; Decoding; Field programmable gate arrays; Firing; Neurons; Real-time systems; Tuning;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Biomedical Circuits and Systems Conference (BioCAS), 2014 IEEE
Conference_Location :
Lausanne
Type :
conf
DOI :
10.1109/BioCAS.2014.6981784
Filename :
6981784
Link To Document :
بازگشت