A novel VLSI iterative divider architecture for fast quotient generation

In this paper, a novel VLSI iterative divider architecture for fast quotient generation that is based on radix-2 non-restoring division is proposed. To speed up the quotient generation, our method makes use of the magnitude difference between the partial dividend and the divisor for the next iteration so that the proper weight of the quotient can be obtained more rapidly than the conventional methods. Our proposed architecture is very simple compared to the multiplication-based methods such as those that are based on Newton-Raphson. Simulation results show that our proposed method can achieve less than half the number of iterations required by the conventional division (i.e. less than nil vs. n, where n is the bit-width of the dividend and the divisor). The proposed architecture has been synthesized in 0.13 mum CMOS standard cell library to demonstrate the delay and the power efficiency.